254 search results - page 8 / 51 » Design and VLSI Implementation of a Unified Synapse-Neuron A... |
TVLSI
1998
13 years 7 months ago
1998
— Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of hig...
ISVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
SIPS
2008
IEEE
14 years 1 months ago
2008
IEEE
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
DATE
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a VLSI Architecture to implement the forward and inverse 2-D Discrete Wavelet Transform (FDWT/IDWT), to compress medical images for storage and retrieval. Loss...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...