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» Design and application of multimodal power gating structures
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DATE
2005
IEEE
127views Hardware» more  DATE 2005»
14 years 2 months ago
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
ISPASS
2005
IEEE
14 years 2 months ago
Studying Thermal Management for Graphics-Processor Architectures
We have previously presented Qsilver, a flexible simulation system for graphics architectures. In this paper we describe our extensions to this system, which we use— instrument...
Jeremy W. Sheaffer, Kevin Skadron, David P. Luebke
MICRO
2003
IEEE
124views Hardware» more  MICRO 2003»
14 years 2 months ago
Optimum Power/Performance Pipeline Depth
The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of pow...
Allan Hartstein, Thomas R. Puzak
CODES
2004
IEEE
14 years 13 days ago
Analytical models for leakage power estimation of memory array structures
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
ESAS
2004
Springer
14 years 2 months ago
Secure AES Hardware Module for Resource Constrained Devices
Abstract. Low power consumption, low gate count, and high throughput are standard design criteria for cryptographic coprocessors designated for resource constrained devices such as...
Elena Trichina, Tymur Korkishko