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» Design and application of multimodal power gating structures
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VTS
2005
IEEE
89views Hardware» more  VTS 2005»
14 years 2 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
BROADNETS
2006
IEEE
14 years 2 months ago
SeeMote: In-Situ Visualization and Logging Device for Wireless Sensor Networks
In this paper we address three challenges that are present when building and analyzing wireless sensor networks (WSN) as part of ubiquitous computing environment: the need for an ...
Leo Selavo, Gang Zhou, John A. Stankovic
ICRA
2009
IEEE
121views Robotics» more  ICRA 2009»
14 years 3 months ago
Differentiated layer design to modify the compliance of soft pads for robotic limbs
— Most of robotic soft pads studied so far were made with a thick layer of homogeneous material shaped around a rigid core; their behavior has been widely investigated in the lit...
Giovanni Berselli, Gabriele Vassura
FPGA
2009
ACM
273views FPGA» more  FPGA 2009»
14 years 3 months ago
A parallel/vectorized double-precision exponential core to accelerate computational science applications
Many natural processes exhibit exponential decay and, consequently, computational scientists make extensive use of e−x in computer simulation experiments. While it is common to ...
Robin Pottathuparambil, Ron Sass
ISLPED
2010
ACM
170views Hardware» more  ISLPED 2010»
13 years 9 months ago
Low-power sub-threshold design of secure physical unclonable functions
The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depen...
Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnapp...