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VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
14 years 7 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
EUROSYS
2008
ACM
14 years 3 months ago
Task activity vectors: a new metric for temperature-aware scheduling
Non-uniform utilization of functional units in combination with hardware mechanisms such as clock gating leads to different power consumptions in different parts of a processor ch...
Andreas Merkel, Frank Bellosa
ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
13 years 6 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
HIPC
2007
Springer
14 years 26 days ago
FFTC: Fastest Fourier Transform for the IBM Cell Broadband Engine
The Fast Fourier Transform (FFT) is of primary importance and a fundamental kernel in many computationally intensive scientific applications. In this paper we investigate its perf...
David A. Bader, Virat Agarwal
DAC
2008
ACM
14 years 7 months ago
Parallelizing CAD: a timely research agenda for EDA
The relative decline of single-threaded processor performance, coupled with the ongoing shift towards on chip parallelism requires that CAD applications run efficiently on paralle...
Bryan C. Catanzaro, Kurt Keutzer, Bor-Yiing Su