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» Design and evaluation of an auto-memoization processor
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MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
14 years 2 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
SIPEW
2009
Springer
127views Hardware» more  SIPEW 2009»
14 years 1 months ago
Investigating Cache Parameters of x86 Family Processors
Abstract. The excellent performance of the contemporary x86 processors is partially due to the complexity of their memory architecture, which therefore plays a role in performance ...
Vlastimil Babka, Petr Tuma
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 3 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...
FPL
2007
Springer
124views Hardware» more  FPL 2007»
14 years 3 months ago
HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation
The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedd...
Koen Bertels, Georgi Kuzmanov, Elena Moscu Panaint...
ISPASS
2008
IEEE
14 years 3 months ago
Metrics for Architecture-Level Lifetime Reliability Analysis
Abstract— This work concerns metrics for evaluating microarchitectural enhancements to improve processor lifetime reliability. A commonly reported reliability metric is mean time...
Pradeep Ramachandran, Sarita V. Adve, Pradip Bose,...