620 search results - page 43 / 124 » Design and evaluation of an auto-memoization processor |
121
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DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
136
Voted
HIPEAC
2005
Springer
15 years 9 months ago
2005
Springer
Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a tradition...
160
Voted
RSP
2003
IEEE
15 years 9 months ago
2003
IEEE
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
156
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SIGMOD
2004
ACM
16 years 4 months ago
2004
ACM
We present new algorithms on commodity graphics processors to perform fast computation of several common database operations. Specifically, we consider operations such as conjunct...
146
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...