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» Design and evaluation of an auto-memoization processor
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VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 4 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
VLSID
2005
IEEE
147views VLSI» more  VLSID 2005»
16 years 4 months ago
Memory-Centric Motion Estimator
In the streaming video processing domain, the only way to meet strict performance and quality requirements and yet to provide the area- and power-wise optimal platform is to apply...
Aleksandar Beric, Ramanathan Sethuraman, Jef L. va...
FPL
2001
Springer
101views Hardware» more  FPL 2001»
15 years 8 months ago
An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars
This paper presents an FPGA-based implementation of a syntactic parser that can process languages generated by almost unrestricted real-life context-free grammars (CFGs). More prec...
Cristian Ciressan, Eduardo Sanchez, Martin Rajman,...
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
15 years 10 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
IPPS
2009
IEEE
15 years 11 months ago
CellMR: A framework for supporting mapreduce on asymmetric cell-based clusters
The use of asymmetric multi-core processors with onchip computational accelerators is becoming common in a variety of environments ranging from scientific computing to enterprise...
M. Mustafa Rafique, Benjamin Rose, Ali Raza Butt, ...