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» Design and evaluation of an auto-memoization processor
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CGO
2008
IEEE
15 years 10 months ago
Compiling for vector-thread architectures
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...
Mark Hampton, Krste Asanovic
DATE
2008
IEEE
139views Hardware» more  DATE 2008»
15 years 10 months ago
Instruction Re-encoding Facilitating Dense Embedded Code
Reducing the code size of embedded applications is one of the important constraint in embedded system design. Code compression can provide substantial savings in terms of size. In...
Talal Bonny, Jörg Henkel
DATE
2007
IEEE
97views Hardware» more  DATE 2007»
15 years 10 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
123
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FPGA
2004
ACM
137views FPGA» more  FPGA 2004»
15 years 9 months ago
Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report
This paper shows a method to verifying the thermal status of complex FPGA-based circuits like microprocessors. Thus, the designer can evaluate if a particular block is working bey...
Sergio López-Buedo, Eduardo I. Boemo
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 9 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock