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» Design and implementation of JPEG encoder IP core
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HEURISTICS
2000
127views more  HEURISTICS 2000»
13 years 7 months ago
Fast, Efficient Equipment Placement Heuristics for Broadband Switched or Internet Router Networks
Planning and designing the next generation of IP router or switched broadband networks seems a daunting challenge considering the many complex, interacting factors affecting the p...
Joel W. Gannett
CODES
2007
IEEE
14 years 1 months ago
Ensuring secure program execution in multiprocessor embedded systems: a case study
Multiprocessor SoCs are increasingly deployed in embedded systems with little or no security features built in. Code Injection attacks are one of the most commonly encountered sec...
Krutartha Patel, Sridevan Parameswaran, Seng Lin S...
PPL
2008
185views more  PPL 2008»
13 years 7 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
14 years 1 months ago
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
Daewook Kim, Manho Kim, Gerald E. Sobelman
ASPDAC
2005
ACM
132views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Automatic synthesis and scheduling of multirate DSP algorithms
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...