97 search results - page 1 / 20 » Design and implementation of JPEG encoder IP core |
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a ...
ARCS
2005
Springer
14 years 27 days ago
2005
Springer
ESTIMEDIA
2004
Springer
14 years 22 days ago
2004
Springer
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Heteregenous multiprocessor SoCs are becoming a reality, largely due to the abundance of transistors, intellectual property cores and powerful design tools. In this project, we ex...