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» Design and implementation of JPEG encoder IP core
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SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
14 years 28 days ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
MIS
2008
Springer
191views Multimedia» more  MIS 2008»
13 years 7 months ago
QoS management and control for an all-IP WiMAX network architecture: Design, implementation and evaluation
The IEEE 802.16 standard provides a specification for a fixed and mobile broadband wireless access system, offering high data rate transmission of multimedia services with differen...
Thomas Michael Bohnert, Marco Castrucci, Nicola Ci...
DAC
2005
ACM
14 years 8 months ago
MP core: algorithm and design techniques for efficient channel estimation in wireless applications
Channel estimation and multiuser detection are enabling technologies for future generations of wireless applications. However, sophisticated algorithms are required for accurate c...
Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timoth...
CAI
2004
Springer
13 years 7 months ago
An Evolvable Combinational Unit for FPGAs
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
Lukás Sekanina, Stepan Friedl
ICASSP
2008
IEEE
14 years 1 months ago
Accurate models for estimating area and power of FPGA implementations
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
Lanping Deng, Kanwaldeep Sobti, Chaitali Chakrabar...