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» Design and implementation of a network simulation system
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DSD
2006
IEEE
107views Hardware» more  DSD 2006»
15 years 10 months ago
A High Level Power Model for the Nostrum NoC
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
Sandro Penolazzi, Axel Jantsch
SIGCSE
2006
ACM
362views Education» more  SIGCSE 2006»
15 years 10 months ago
Chirp on crickets: teaching compilers using an embedded robot controller
Traditionally, the topics of compiler construction and language processing have been taught as an elective course in Computer Science curricula. As such, students may graduate wit...
Li Xu, Fred G. Martin
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 9 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
TVLSI
2010
14 years 10 months ago
Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding
By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density ad...
Shu Li, Tong Zhang
SIGMOD
2009
ACM
157views Database» more  SIGMOD 2009»
16 years 4 months ago
FPGA: what's in it for a database?
While there seems to be a general agreement that next years' systems will include many processing cores, it is often overlooked that these systems will also include an increa...
Jens Teubner, René Müller