A High Level Power Model for the Nostrum NoC

We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. The model, which from now on will be called Nos-HPM (Nostrum High-Level Power Model) allows a fast power analysis and is accurate within 5%. System simulations with Nos-HPM run up to 500 times faster than with Power Compiler for a 4 x 4 network. We find a maximum power consumption of 0.7 W for a 4 x 4 mesh and 3.5 W for an 8 x 8 mesh, both implemented in 0.18µm UPC CMOS technology. In the worst case the average energy per cycle for a 128-bit packet is 508 pJ, while it is 20 pJ for a payload byte. The power consumption of all the links is equivalent or slightly higher than the power consumption of all the switches. A comparison between our results and some related work is also presented.

• Type: Conference
• Year: 2006
• Where: DSD
• Authors: Sandro Penolazzi, Axel Jantsch
• Keywords: DSD 2006, Hardware, Power Compiler, Power Consumption, Power Model