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ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
15 years 10 months ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
ICRA
2005
IEEE
184views Robotics» more  ICRA 2005»
15 years 9 months ago
3D Virtual Prototyping of Home Service Robots Using ASADAL/OBJ
– Typical robot development requires that hardware be mostly functional before significant software development begins. Utilizing virtual prototype of hardware and its environmen...
Kyo Chul Kang, Moonzoo Kim, Jaejoon Lee, Byungkil ...
ICSE
2007
IEEE-ACM
16 years 3 months ago
Randomized Differential Testing as a Prelude to Formal Verification
Most flight software testing at the Jet Propulsion Laboratory relies on the use of hand-produced test scenarios and is executed on systems as similar as possible to actual mission...
Alex Groce, Gerard J. Holzmann, Rajeev Joshi
ICCAD
2008
IEEE
109views Hardware» more  ICCAD 2008»
16 years 22 days ago
Verifying external interrupts of embedded microprocessor in SoC with on-chip bus
—The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with othe...
Fu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang
GLOBECOM
2008
IEEE
15 years 10 months ago
Joint Channel and Mismatch Correction for OFDM Reception with Time-interleaved ADCs: Towards Mostly Digital MultiGigabit Transce
— Time-interleaved (TI) analog-to-digital converters (ADCs) are a promising architecture for realizing the highspeed ADCs required to implement “mostly digital” receivers for...
P. Sandeep, Upamanyu Madhow, Munkyo Seo, Mark J. W...