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ISCA
2005
IEEE
128views Hardware» more  ISCA 2005»
15 years 10 months ago
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures
: The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical...
Steven Balensiefer, Lucas Kreger-Stickles, Mark Os...
ISCC
2005
IEEE
107views Communications» more  ISCC 2005»
15 years 10 months ago
FTSE: The FNP-Like TCAM Searching Engine
As the Internet grows at a very rapid pace, so does the incidence of attack events and documented unlawful intrusions. The Network Intrusion Detection Systems (NIDSes) are designe...
Rong-Tai Liu, Chia-Nan Kao, Hung-Shen Wu, Ming-Cha...
MEMOCODE
2005
IEEE
15 years 10 months ago
Extended abstract: a race-free hardware modeling language
We describe race-free properties of a hardware description language called GEZEL. The language describes networks of cycle-true finite-state-machines with datapaths (FSMDs). We de...
Patrick Schaumont, Sandeep K. Shukla, Ingrid Verba...
MICRO
2005
IEEE
144views Hardware» more  MICRO 2005»
15 years 10 months ago
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardw...
Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vi...
ISLPED
2005
ACM
102views Hardware» more  ISLPED 2005»
15 years 10 months ago
Snug set-associative caches: reducing leakage power while improving performance
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
Jia-Jhe Li, Yuan-Shin Hwang
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