Snug set-associative caches: reducing leakage power while improving performance

As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Several techniques have already been proposed to reduce leakage power by turning off unused cache lines. However, they all have to pay the price of performance degradation. This paper presents a cache architecture, the Snug Set-Associative (SSA) cache, that does not only cut most of static power dissipation but also reduces execution times. The SSA cache reduces leakage power by implementing the minimum set-associative scheme, which only activates the minimal numbers of ways in each cache set, while the performance losses incurred by this scheme are compensated by the base-offset load/store queues. These two techniques are both developed based on the principle of locality and they work together nicely—experimental results show that the minimum set-associative scheme can cut static power consumption of the L1 ...

• Type: Conference
• Year: 2005
• Where: ISLPED
• Authors: Jia-Jhe Li, Yuan-Shin Hwang
• Keywords: Cache, ISLPED 2005, Leakage Power, Static Power Dissipation