13101 search results - page 2482 / 2621 » Design and implementation of an |
ISCA
2009
IEEE
14 years 3 months ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
Cache blocks often exhibit a small number of uses during their life time in the last-level cache. Past research has exploited this property in two different ways. First, replacem...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor designs providing diminishing returns, the industry has moved beyond single-core micr...