584 search results - page 8 / 117 » Design and implementation of correlating caches |
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
ICDCS
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper, we describe the design and implementation of an integrated architecture for cache systems that scale to hundreds or thousands of caches with thousands to millions o...
USENIX
1996
13 years 8 months ago
1996
: This paper discussesthedesignandperformance of a hierarchical proxy-cache designed to make Internet information systems scale better. The design was motivated by our earlier trac...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
3D integration is an emergent technology that has the potential to greatly increase device density while simultaneously providing faster on-chip communication. 3D fabrication invo...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multi...