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TCAD
1998
125views more  TCAD 1998»
15 years 4 months ago
Test-point insertion: scan paths through functional logic
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
FPL
2010
Springer
139views Hardware» more  FPL 2010»
15 years 2 months ago
Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA
A Multivariate Gaussian random number generator (MVGRNG) is an essential block for many hardware designs, including Monte Carlo simulations. These simulations are usually used in a...
Chalermpol Saiprasert, Christos-Savvas Bouganis, G...
131
Voted
DAC
2006
ACM
16 years 5 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
145
Voted
TAMODIA
2007
15 years 5 months ago
Exploring Usability Needs by Human-Computer Interaction Patterns
Abstract. Covering quality aspects such as usability through the software development life cycle is challenging. These “-ilities” are generally difficult to grasp and usually ...
Markus Specker, Ina Wentzlaff
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Crosstalk analysis using reconvergence correlation
Abstract— In the UDSM era, crosstalk is an area of considerable concern for designers, as it can have a considerable impact on the yield, both in terms of functionality and opera...
Sachin Shrivastava, Rajendra Pratap, Harindranath ...