In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature...
With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence o...
Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq ...
This paper develops analytical models to predict the throughput and the response time of a replicated database using measurements of the workload on a standalone database. These m...
Sameh Elnikety, Steven G. Dropsho, Emmanuel Cecche...
We present a load-balancing technique that exploits the temporal coherence, among successive computation phases, in mesh-like computations to be mapped on a cluster of processors....
Biagio Cosenza, Gennaro Cordasco, Rosario De Chiar...
Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of th...