59 search results - page 9 / 12 » Design for Verification in System-level Models and RTL |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
roperty Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines Dong Wang , Pei-Hsin Ho , Jiang Long , James Kukula Yunshan Zhu , Tony Ma , Robert D...
FDL
2007
IEEE
14 years 1 months ago
2007
IEEE
Since its first release the system level language SystemC had a significant impact on various areas in VLSI-CAD. One remarkable benefit of SystemC lies in the of abstraction le...
CAISE
2010
Springer
13 years 8 months ago
2010
Springer
For enterprises it has become crucial to check compliance of their business processes with certain rules such as medical guidelines or financial regulations. When automating compli...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
ng precision of abstract SystemC models using the SystemC Verification Standard Franco Carbognani1 , Christopher K. Lennard2 , C. Norris Ip3 , Allan Cochrane2 , Paul Bates2 1 Caden...