231 search results - page 17 / 47 » Design issues for dynamic voltage scaling |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
This paper presents an optimal procrastinating voltage scheduling (OP-DVS) for hard real-time systems using stochastic workload information. Algorithms are presented for both sing...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Using additional store-checkpoinsts (SCPs) and compare-checkpoints (CCPs), we present an adaptive checkpointing for double modular redundancy (DMR) in this paper. The proposed app...
MICRO
2003
IEEE
14 years 19 days ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
SAC
2009
ACM
14 years 2 months ago
2009
ACM
In this paper, we consider minimizing the system-level energy consumption through dynamic voltage scaling for embedded devices, while a) allowing concurrent access to shared objec...
ISLPED
2004
ACM
14 years 24 days ago
2004
ACM
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by dee...