82 search results - page 10 / 17 » Design of Asynchronous Controllers with Delay Insensitive In... |
ESM
1998
13 years 8 months ago
1998
This paper introduces a dynamics simulator designed to aid the development of control algorithms for biologically inspired robots. We describe the simulator and a two-tier framewo...
ISVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
ASYNC
2000
IEEE
13 years 12 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
ARVLSI
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...