Most future large-scale sensor networks are expected to follow a two-tier architecture which consists of resource-rich master nodes at the upper tier and resource-poor sensor node...
Mandated requirements to share information across different sensitivity domains necessitate the design of distributed architectures to enforce information flow policies while pr...
Cynthia E. Irvine, Thuy D. Nguyen, David J. Shiffl...
Discrete-event packet-level network simulation is well-known and widely used. Network emulation is a hybrid approach that combines real elements of a deployed networked applicatio...
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...