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ASPDAC
2005
ACM
101views Hardware» more  ASPDAC 2005»
13 years 9 months ago
A clustering technique to optimize hardware/software synchronization
— In this paper we present a scheme for reducing the amount of synchronization overhead needed between components, after HW/SW partitioning, to preserve the original control flo...
Junyu Peng, Samar Abdi, Daniel Gajski
DATE
2005
IEEE
152views Hardware» more  DATE 2005»
14 years 1 months ago
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips
Technology Roadmap for Semiconductors (ITRS) clearly identifies the integration of electrochemical and electrobiological techniques as one of the system-level design challenges tha...
Fei Su, Krishnendu Chakrabarty
PPL
2008
185views more  PPL 2008»
13 years 7 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Software Performance Estimation in MPSoC Design
- Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration. Estimation of software performance is essential in current software-...
Márcio Oyamada, Flávio Rech Wagner, ...
GLVLSI
2003
IEEE
140views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Exploiting multiple functionality for nano-scale reconfigurable systems
It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a res...
Paul Beckett