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HPCA
2005
IEEE
14 years 1 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
PACS
2004
Springer
146views Hardware» more  PACS 2004»
14 years 27 days ago
An Optimized Front-End Physical Register File with Banking and Writeback Filtering
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
Miquel Pericàs, Rubén Gonzále...
ISORC
2011
IEEE
12 years 11 months ago
A Time-Predictable Object Cache
—Static cache analysis for data allocated on the heap is practically impossible for standard data caches. We propose a distinct object cache for heap allocated data. The cache is...
Martin Schoeberl
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
14 years 25 days ago
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
Alberto Macii, Enrico Macii, Fabrizio Crudo, Rober...
MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
13 years 11 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin