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» Design of a WCET-Aware C Compiler
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DATE
2006
IEEE
113views Hardware» more  DATE 2006»
14 years 2 months ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
Hanno Scharwächter, Manuel Hohenauer, Rainer ...
EUROPAR
2005
Springer
14 years 2 months ago
SPC-XML: A Structured Representation for Nested-Parallel Programming Languages
Nested-parallelism programming models, where the task graph associated to a computation is series-parallel, present good analysis properties that can be exploited for scheduling, c...
Arturo González-Escribano, Arjan J. C. van ...
FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
14 years 2 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...
LCPC
2005
Springer
14 years 1 months ago
A Language for the Compact Representation of Multiple Program Versions
Abstract. As processor complexity increases compilers tend to deliver suboptimal performance. Library generators such as ATLAS, FFTW and SPIRAL overcome this issue by empirically s...
Sébastien Donadio, James C. Brodman, Thomas...
DAC
2009
ACM
14 years 1 months ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers