253 search results - page 10 / 51 » Design of a logic element for implementing an asynchronous F... |
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
ROBIO
2006
IEEE
14 years 1 months ago
2006
IEEE
- The implementation of inverse kinematics and servo controller for robot manipulator using FPGA (Field Programmer Gate Array) is investigated in this paper. Firstly, the mathemati...
TVLSI
2008
13 years 7 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
ISMVL
1997
IEEE
13 years 12 months ago
1997
IEEE
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...