253 search results - page 11 / 51 » Design of a logic element for implementing an asynchronous F... |
IPPS
1999
IEEE
13 years 12 months ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...
FTEDA
2007
13 years 7 months ago
2007
Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their archite...