Sciweavers

253 search results - page 44 / 51
» Design of a logic element for implementing an asynchronous F...
Sort
View
ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
14 years 1 months ago
A reconfigurable architecture for scanning biosequence databases
—Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
Timothy F. Oliver, Bertil Schmidt, Douglas L. Mask...
ARCS
2006
Springer
13 years 11 months ago
Minimising the Hardware Resources for a Cellular Automaton with Moving Creatures
: Given is the following "creature's exploration problem": n creatures are moving around in an unknown environment in order to visit all cells in shortest time. This...
Mathias Halbach, Rolf Hoffmann
RTSS
2006
IEEE
14 years 1 months ago
MCGREP - A Predictable Architecture for Embedded Real-Time Systems
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...
Jack Whitham, Neil C. Audsley
MBEES
2010
13 years 9 months ago
Towards Architectural Programming of Embedded Systems
: Integrating architectural elements with a modern programming language is essential to ensure a smooth combination of architectural design and programming. In this position statem...
Arne Haber, Jan Oliver Ringert, Bernhard Rumpe
CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...