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» Design of clocked circuits using UML
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FDL
2005
IEEE
14 years 1 months ago
UML/XML based approach to hierarchical AMS Synthesis
This paper explores the suitability of UML techniques for defining hierarchical relationships in AMS (analogue and mixed-signal) circuit blocks, and XML for storing soft AMS IP de...
Ian O'Connor, Faress Tissafi-Drissi, G. Revy, Fr&e...
APCCAS
2006
IEEE
206views Hardware» more  APCCAS 2006»
14 years 1 months ago
Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory
—A pre-comparison scheme is designed by using the NOR-type 10T content addressable memory (CAM) between the match line circuits and the pre-charging circuits. Thereby, several bi...
Po-Tsang Huang, Wei-Keng Chang, Wei Hwang
ICCAD
2000
IEEE
77views Hardware» more  ICCAD 2000»
14 years 7 days ago
Improving the Proportion of At-Speed Tests in Scan BIST
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...
Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janus...
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
14 years 1 months ago
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen
ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
14 years 4 months ago
Branch Merge Reduction of RLCM Networks
— In this paper we consider the problem of finding a smaller RLCM circuit that approximately replicates the behavior (up to a certain frequency) of a given RLCM circuit. Targeted...
Bernard N. Sheehan