195 search results - page 25 / 39 » Design of clocked circuits using UML |
ARVLSI
1997
IEEE
14 years 2 days ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
ICCD
1997
IEEE
13 years 11 months ago
1997
IEEE
Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practica...
ENTCS
2006
13 years 7 months ago
2006
A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in t...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
DATE
1999
IEEE
14 years 5 days ago
1999
IEEE
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...