195 search results - page 27 / 39 » Design of clocked circuits using UML |
FPGA
2010
ACM
13 years 5 months ago
2010
ACM
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
ICCAD
1997
IEEE
14 years 2 days ago
1997
IEEE
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
DAC
1997
ACM
14 years 1 days ago
1997
ACM
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...