—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
We study Life-like cellular automaton rule B2/S2345. This automaton exhibits a chaotic behavior yet capable for purposeful computation. The automaton implements Boolean gates via p...