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ITC
2002
IEEE
81views Hardware» more  ITC 2002»
14 years 21 days ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
VTS
1995
IEEE
100views Hardware» more  VTS 1995»
13 years 11 months ago
Transformed pseudo-random patterns for BIST
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
Nur A. Touba, Edward J. McCluskey
FCCM
2004
IEEE
141views VLSI» more  FCCM 2004»
13 years 11 months ago
Deep Packet Filter with Dedicated Logic and Read Only Memories
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...
Young H. Cho, William H. Mangione-Smith
FPGA
2005
ACM
156views FPGA» more  FPGA 2005»
14 years 1 months ago
Design of programmable interconnect for sublithographic programmable logic arrays
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
André DeHon
UC
2010
Springer
13 years 5 months ago
Majority Adder Implementation by Competing Patterns in Life-Like Rule B2/S2345
We study Life-like cellular automaton rule B2/S2345. This automaton exhibits a chaotic behavior yet capable for purposeful computation. The automaton implements Boolean gates via p...
Genaro Juárez Martínez, Kenichi Mori...