15 search results - page 1 / 3 » Design rule optimization of regular layout for leakage reduc... |
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
TIM
2010
13 years 2 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
DATE
2005
IEEE
2005
IEEE
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
14 years 1 months ago
This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switc...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...