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» Design space exploration for 3D architectures
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DAC
2000
ACM
14 years 9 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
IEEECIT
2005
IEEE
14 years 2 months ago
A Performance and Power Co-optimization Approach for Modern Processors
In embedded systems, performance and power are important inter-related issues that cannot be decoupled. Expensive and extensive simulations in a processor design space are usually...
Yongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh
DUX
2007
14 years 17 days ago
180 x 120: designing alternate location systems
Using 180 RFID tags to track and plot locations over time, guests to an event at the San Francisco Museum of Modern Art (SFMOMA) collectively constructed a public visualization of...
Eric Paulos, Anthony Burke, Tom Jenkins, Karen Mar...
FPGA
2008
ACM
129views FPGA» more  FPGA 2008»
13 years 10 months ago
Efficient ASIP design for configurable processors with fine-grained resource sharing
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...
Quang Dinh, Deming Chen, Martin D. F. Wong
DATE
2009
IEEE
132views Hardware» more  DATE 2009»
14 years 3 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...