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ICCD
2006
IEEE
118views Hardware» more  ICCD 2006»
16 years 3 months ago
A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...
Jinwen Xi, Peixin Zhong
SBACPAD
2003
IEEE
137views Hardware» more  SBACPAD 2003»
15 years 11 months ago
Exploring Memory Hierarchy with ArchC
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
MOBIHOC
2008
ACM
16 years 5 months ago
Exploring semantic interference in heterogeneous sensor networks
As the use of wireless sensor networks expands, there will be multiple, independent networks operating in the same physical space. These networks will run heterogeneous applicatio...
Laura Marie Feeney
CODES
2003
IEEE
15 years 11 months ago
A multiobjective optimization model for exploring multiprocessor mappings of process networks
In the Sesame framework, we develop a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes se...
Cagkan Erbas, Selin C. Erbas, Andy D. Pimentel
ARCS
2006
Springer
15 years 9 months ago
Estimating Energy Consumption for an MPSoC Architectural Exploration
Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until t...
Rabie Ben Atitallah, Smaïl Niar, Alain Greine...