System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
We preseM an algorithm for compiler-driven regisrer mme adjustment with rhe main goal of power minimization on instruction fetch und mgisterjile access. In mosr instruction set ar...
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
In traditional distributed embedded system designs, control information is often replicated across several processes and kept coherent by application-specific mechanisms. Conseque...
Pai H. Chou, Ken Hines, Kurt Partridge, Gaetano Bo...
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
Yosr Jarraya, Andrei Soeanu, Mourad Debbabi, Fawzi...