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» Design with race-free hardware semantics
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MEMOCODE
2003
IEEE
14 years 26 days ago
MoDe: A Method for System-Level Architecture Evaluation
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
Jan Romberg, Oscar Slotosch, Gabor Hahn
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
14 years 4 months ago
Compiler-Based Register Name Adjustment for Low-Power Embedded Processors
We preseM an algorithm for compiler-driven regisrer mme adjustment with rhe main goal of power minimization on instruction fetch und mgisterjile access. In mosr instruction set ar...
Peter Petrov, Alex Orailoglu
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
14 years 1 months ago
Automated Synthesis of Assertion Monitors using Visual Specifications
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
Ambar A. Gadkari, S. Ramesh
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
13 years 12 months ago
Control generation for embedded systems based on composition of modal processes
In traditional distributed embedded system designs, control information is often replicated across several processes and kept coherent by application-specific mechanisms. Conseque...
Pai H. Chou, Ken Hines, Kurt Partridge, Gaetano Bo...
ECBS
2007
IEEE
145views Hardware» more  ECBS 2007»
13 years 11 months ago
Automatic Verification and Performance Analysis of Time-Constrained SysML Activity Diagrams
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
Yosr Jarraya, Andrei Soeanu, Mourad Debbabi, Fawzi...