This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
: It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network ...
Negative Bias Temperature Instability (NBTI) has been identified as a major and critical reliability issue for PMOS devices in nano-scale designs. It manifests as a negative thres...
Kewal K. Saluja, Shriram Vijayakumar, Warin Sootka...
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...