397 search results - page 33 / 80 » Designing Fast Asynchronous Circuits |
ASIAMS
2008
IEEE
14 years 4 months ago
2008
IEEE
A carry-select adder(CSA) can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders to reduce the area and power but w...
VLSISP
2002
13 years 9 months ago
2002
3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. Th...
ASYNC
2002
IEEE
14 years 2 months ago
2002
IEEE
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
ASPDAC
2007
ACM
14 years 1 months ago
2007
ACM
This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64TM microprocessor with 90nm CMOS technology. It focuses on the newly adopted t...
ISLPED
1995
ACM
14 years 1 months ago
1995
ACM
We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market...