Sciweavers

397 search results - page 59 / 80
» Designing Fast Asynchronous Circuits
Sort
View
ISPD
2005
ACM
145views Hardware» more  ISPD 2005»
14 years 1 months ago
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
In this paper, we present a hierarchical ratio partitioning based placement algorithm for large-scale mixed-size designs. The placement algorithm consists of three steps: global p...
Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Ya...
ISPD
2012
ACM
234views Hardware» more  ISPD 2012»
12 years 3 months ago
MAPLE: multilevel adaptive placement for mixed-size designs
We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global...
Myung-Chul Kim, Natarajan Viswanathan, Charles J. ...
DAC
1999
ACM
13 years 12 months ago
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
Alex Doboli, Adrián Núñez-Ald...
ARVLSI
1999
IEEE
112views VLSI» more  ARVLSI 1999»
13 years 12 months ago
Architectural Considerations for Application-Specific Counterflow Pipelines
Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for ...
Bruce R. Childers, Jack W. Davidson
DAC
2004
ACM
14 years 29 days ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh