397 search results - page 5 / 80 » Designing Fast Asynchronous Circuits |
ASYNC
2005
IEEE
14 years 1 months ago
2005
IEEE
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a ...
CHES
2003
Springer
14 years 21 days ago
2003
Springer
Abstract. Balanced asynchronous circuits have been touted as a superior replacement for conventional synchronous circuits. To assess these claims, we have designed, manufactured an...
FPL
2003
Springer
14 years 21 days ago
2003
Springer
We discuss high-performance programmable asynchronous pipeline arrays (PAPAs). These pipeline arrays are coarse-grain field programmable gate arrays (FPGAs) that realize high data...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
An asynchronous router for QNoC (Quality-of service NoC) is presented. It combines multiple service levels (SL) with multiple equal-priority virtual channels (VC) within each leve...