397 search results - page 78 / 80 » Designing Fast Asynchronous Circuits |
ISCA
2002
IEEE
14 years 12 days ago
2002
IEEE
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
This paper proposes a framework for (signal) interconnect power optimization at the global routing stage. In a typical design flow, the primary objective of global routing is mini...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmab...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
Global routing is an important step in the physical design process. In this paper, we propose a new global routing algorithm Archer, which resolves some of the most common problem...