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» Designing High Bandwidth On-Chip Caches
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VIS
2007
IEEE
101views Visualization» more  VIS 2007»
14 years 8 months ago
Random-Accessible Compressed Triangle Meshes
With the exponential growth in size of geometric data, it is becoming increasingly important to make effective use of multilevel caches, limited disk storage, and bandwidth. As a r...
Sung-Eui Yoon, Peter Lindstrom
IJNSEC
2007
204views more  IJNSEC 2007»
13 years 7 months ago
Enhanced DSR for MANET with Improved Secured Route Discovery and QoS
Mobile Ad hoc NETwork (MANET) comprises of nodes, which are free to move randomly, yet cooperate to forward packets between source and destination over a multi-hop wireless networ...
Anil Rawat, Prakash Dattatraya Vyavahare, Ashwani ...
ICCD
2005
IEEE
108views Hardware» more  ICCD 2005»
14 years 4 months ago
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...
Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Danie...
IPPS
2003
IEEE
14 years 24 days ago
Simulation of Dynamic Data Replication Strategies in Data Grids
Data Grids provide geographically distributed resources for large-scale data-intensive applications that generate large data sets. However, ensuring efficient access to such huge...
Houda Lamehamedi, Zujun Shentu, Boleslaw K. Szyman...
ISCA
2003
IEEE
101views Hardware» more  ISCA 2003»
14 years 24 days ago
Overcoming the Limitations of Conventional Vector Processors
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
Christoforos E. Kozyrakis, David A. Patterson