63 search results - page 4 / 13 » Designing High Bandwidth On-Chip Caches |
SOSP
2001
ACM
14 years 4 months ago
2001
ACM
Users rarely consider running network file systems over slow or wide-area networks, as the performance would be unacceptable and the bandwidth consumption too high. Nonetheless, ...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
HIPEAC
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a tradition...
CLUSTER
2006
IEEE
14 years 1 months ago
2006
IEEE
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
IEEEPACT
2003
IEEE
14 years 24 days ago
2003
IEEE
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...