85 search results - page 7 / 17 » Designing Memory Subsystems Resilient to Process Variations |
ICML
1998
IEEE
14 years 8 months ago
1998
IEEE
This paper introduces a new algorithm, Q2, foroptimizingthe expected output ofamultiinput noisy continuous function. Q2 is designed to need only a few experiments, it avoids stron...
LCTRTS
2010
Springer
14 years 2 months ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
ICDCS
2006
IEEE
14 years 1 months ago
2006
IEEE
Timing failures refer to a situation where the environment in which a system operates does not behave as expected regarding the timing assumptions, that is, the timing constraints...
WSC
2008
13 years 10 months ago
2008
This research presents an integrated simulation modelingDesign For Six Sigma (DFSS) framework to study the design and process issues in a server manufacturing environment. The ser...