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ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
14 years 18 days ago
Data marshaling for multi-core architectures
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
M. Aater Suleman, Onur Mutlu, José A. Joao,...
ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
12 years 11 months ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas
IPPS
2010
IEEE
13 years 5 months ago
On the importance of bandwidth control mechanisms for scheduling on large scale heterogeneous platforms
We study three scheduling problems (file redistribution, independent tasks scheduling and broadcasting) on large scale heterogeneous platforms under the Bounded Multi-port Model. I...
Olivier Beaumont, Hejer Rejeb
LCTRTS
2007
Springer
14 years 1 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
PPOPP
1990
ACM
13 years 11 months ago
Concurrent Aggregates (CA)
Toprogrammassivelyconcurrent MIMDmachines, programmersneed tools for managingcomplexity. One important tool that has been used in the sequential programmingworld is hierarchies of...
Andrew A. Chien, William J. Dally