In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
Capturing and using design rationale is becoming a hot topic for software architects, as architectural design decisions are now considered first class entities that should be reco...
During the past five years, our research group worked with a group of public school teachers to define, develop, and assess network-based support for collaborative learning in mid...
John M. Carroll, George Chin Jr., Mary Beth Rosson...
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Fourth-generation wireless communication systems (4G) will have totally different requirements than what front-end designers have been coping with up to now. Designs must be targe...