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CDES
2006
158views Hardware» more  CDES 2006»
13 years 8 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
KBSE
2008
IEEE
14 years 1 months ago
Effort Estimation in Capturing Architectural Knowledge
Capturing and using design rationale is becoming a hot topic for software architects, as architectural design decisions are now considered first class entities that should be reco...
Rafael Capilla, Francisco Nava, Carlos Carrillo
ACMDIS
2000
ACM
13 years 11 months ago
The Development of Cooperation: Five Years of Participatory Design in the Virtual School
During the past five years, our research group worked with a group of public school teachers to define, develop, and assess network-based support for collaborative learning in mid...
John M. Carroll, George Chin Jr., Mary Beth Rosson...
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
13 years 11 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
DAC
2003
ACM
13 years 12 months ago
4G terminals: how are we going to design them?
Fourth-generation wireless communication systems (4G) will have totally different requirements than what front-end designers have been coping with up to now. Designs must be targe...
Jan Craninckx, Stéphane Donnay