Sciweavers

122 search results - page 13 / 25
» Designing a Memory Module Tester
Sort
View
ICC
2009
IEEE
135views Communications» more  ICC 2009»
13 years 6 months ago
A Discrete Channel Model for Capturing Memory and Soft-Decision Information: A Capacity Study
A discrete (binary-input 2q -ary output) communication channel with memory is introduced with the objective to judiciously capture both the statistical memory and the soft-decision...
Cecilio Pimentel, Fady Alajaji
MICRO
2006
IEEE
111views Hardware» more  MICRO 2006»
14 years 3 months ago
Memory Prefetching Using Adaptive Stream Detection
We present Adaptive Stream Detection, a simple technique for modulating the aggressiveness of a stream prefetcher to match a workload’s observed spatial locality. We use this co...
Ibrahim Hur, Calvin Lin
DAC
1998
ACM
14 years 10 months ago
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
14 years 3 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
TVLSI
2010
13 years 3 months ago
Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding
By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density ad...
Shu Li, Tong Zhang