122 search results - page 19 / 25 » Designing a Memory Module Tester |
HPCA
2000
IEEE
14 years 1 months ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clock...
ICMCS
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
ASYNC
2002
IEEE
14 years 1 months ago
2002
IEEE
We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not...
SASP
2009
IEEE
14 years 3 months ago
2009
IEEE
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...